Avalanche energy handling capable III-nitride transistors
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Dec 15, 2016
filing date -
May 3, 2013
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Abstract
A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
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