Integrated process and structure to form III-V channel for sub-7nm CMOS devices
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United States of America Patent
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Jan 9, 2018
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app pub date -
Sep 27, 2016
filing date -
Nov 9, 2015
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Abstract
Embodiments described herein generally relate to methods and structures for forming precise fins comprising Group III-V elements on a silicon substrate. A buffer layer is deposited in a trench formed in the dielectric material on a substrate. An isolation layer is then deposited over the buffer layer. A portion of the isolation layer is removed allowing for a precisely sized Group III-V channel layer to be deposited on the isolation layer.
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