High-voltage transistor architectures, processes of forming same, and systems containing same
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Mar 30, 2015
filing date -
Aug 18, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
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- 7 Age
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