Nanowire transistors having multiple threshold voltages
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United States of America Patent
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Jan 9, 2018
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Mar 8, 2017
filing date -
Mar 8, 2017
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Abstract
Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.
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