Systems and methods for testing and packaging a superconducting chip
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Dec 17, 2013
filing date -
Dec 17, 2012
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.
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International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 6 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 9, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 9, 2029 |
