Interconnect structure for stacked device and method
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United States of America Patent
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Jan 9, 2018
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app pub date -
May 27, 2016
filing date -
Mar 15, 2013
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Abstract
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
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