Method of forming a device including a floating gate electrode and a layer of ferroelectric material
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United States of America Patent
Stats
-
Jan 9, 2018
Issued Date -
N/A
app pub date -
May 23, 2016
filing date -
Aug 26, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.
First Claim
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International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 9 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
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