Method for FinFET integrated with capacitor
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United States of America Patent
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Jan 9, 2018
Grant Date -
Jun 30, 2016
app pub date -
Mar 9, 2016
filing date -
Apr 11, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first and second portions. A top surface of the first portion is lower than a top surface of the second portion. The semiconductor structure further comprises fin active regions; conductive features on the fin active regions and the STI feature; and dielectric features separating the conductive features from the fin active regions. The semiconductor structure further comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features.
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