Memory device having cell over periphery structure and memory package including the same
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Sep 22, 2016
filing date -
Dec 17, 2015
priority date (Note) -
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Abstract
A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.
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