Power module package having patterned insulation metal substrate
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United States of America Patent
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Jan 9, 2018
Grant Date -
Nov 2, 2017
app pub date -
Apr 29, 2016
filing date -
Apr 29, 2016
priority date (Note) -
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Abstract
A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.
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