Use of an external getter to reduce package pressure

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United States of America Patent

PATENT NO 9865519
SERIAL NO

15402329

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Abstract

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A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.

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Patent Owner(s)

Patent OwnerAddress
RAYTHEON COMPANY50 APPLE HILL DRIVE TEWKSBURY MA 01876

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Black, Stephen H Tennesse Ridge, US 39 295
Kennedy, Adam M Santa Barbara, US 42 302

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