Device and methods for high-K and metal gate slacks
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United States of America Patent
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Jan 9, 2018
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app pub date -
Dec 18, 2015
filing date -
Apr 26, 2012
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Abstract
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
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