Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Jul 7, 2016
filing date -
Mar 7, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
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International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 9, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 9, 2029 |
