Method of fine line space resolution lithography for integrated circuit features using double patterning technology
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Mar 21, 2017
filing date -
Aug 16, 2013
priority date (Note) -
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Abstract
A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
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