Package and method for integration of heterogeneous integrated circuits
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United States of America Patent
Stats
-
Jan 9, 2018
Issued Date -
N/A
app pub date -
Jul 29, 2016
filing date -
Aug 30, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
First Claim
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Family
International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 9, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 9, 2029 |
