Phase change memory device and method of operation
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United States of America Patent
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Jan 9, 2018
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N/A
app pub date -
Mar 31, 2017
filing date -
Aug 11, 2016
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Abstract
A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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