Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power

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United States of America Patent

PATENT NO 9865316
SERIAL NO

15003444

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Abstract

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A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

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Patent Owner(s)

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QUALCOMM INCORPORATED5775 MOREHOUSE DRIVE SAN DIEGO CA 92121-1714

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boda, Veerabhadra Rao East Godavari, IN 5 10
Gupta, Sharad Kumar Bangalore, IN 28 96
Narasimhan, Mukund Bangalore, IN 41 369

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