Compensation of deterministic crosstalk in memory system
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Dec 2, 2016
filing date -
Dec 4, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes a detector circuit and a receiver circuit. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The receiver circuit may be configured to initialize an equalizer circuit configured to compensate for deterministic crosstalk coupled between a data line and a data strobe line to provide an increased margin.
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Patent Citation Ranking
- 1 Citation Count
- G11C Class
- 17.97 % this patent is cited more than
- 7 Age
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