Low-profile real-time location system tag

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United States of America Patent

PATENT NO 9864946
SERIAL NO

15455643

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An example disclosed example includes a housing; a printed circuit board carried by the housing and including an antenna feed aperture; a logic circuit disposed on a first side of the printed circuit board, the logic circuit to generate blink data comprising pulses and data; an antenna disposed on a second side of the printed circuit board, the antenna in electrical communication with the logic circuit via the antenna feed aperture, the antenna configured to transmit the blink data; a dielectric potting material to protect the logic circuit; and a seal to cover the antenna feed aperture, the seal to prevent the dielectric potting material from entering the antenna feed aperture.

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Patent Owner(s)

Patent OwnerAddress
JPMORGAN CHASE BANK N A AS COLLATERAL AGENTCIB DMO WLO MAIL CODE NY1C413 4 CMC BROOKLYN NY 11245-0001

International Classification(s)

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  • 2017 Application Filing Year
  • G06K Class
  • 13824 Applications Filed
  • 10143 Patents Issued To-Date
  • 73.38 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Richley, Edward A Gaithersburg, US 71 2746

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Patent Citation Ranking

  • 2 Citation Count
  • G06K Class
  • 20.79 % this patent is cited more than
  • 7 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges10163210382126754415433901 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8091 - 100100 +02004006008001000120014001600180020002200240026002800300032003400

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