Method and apparatus for power reduction in a multi-threaded mode
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 9, 2018
Issued Date -
N/A
app pub date -
Aug 17, 2016
filing date -
Aug 17, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory is described. The apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration, and a second comparator bank including a second plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration. An input virtual address to each comparator bank maintains its previous value for when a corresponding thread is not selected.
First Claim
Other Claims data not available
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H04L Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 9, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 9, 2029 |