Cache coherent system including master-side filter and data processing system including same
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United States of America Patent
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Jan 9, 2018
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N/A
app pub date -
Jun 30, 2016
filing date -
Jul 1, 2015
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Abstract
An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.
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