Methods of operating memory systems for sub-block erase operation
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United States of America Patent
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Jan 9, 2018
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app pub date -
Jan 20, 2016
filing date -
Jan 21, 2015
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Abstract
A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.
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