Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof
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United States of America Patent
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Jan 2, 2018
Grant Date -
Dec 14, 2017
app pub date -
Jun 8, 2017
filing date -
Jun 13, 2016
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Abstract
A successive approximation register (SAR) analog-to-digital converter (ADC) comprises a comparator for generating a comparison value according to an analog signal; a SAR, coupled to the comparator, comprises N memory units, each memory unit storing a control value and the N control values being related to the comparison value, N being an integer greater than two; and a thermometer-coded DAC, which generates the analog signal and is coupled to the comparator and the SAR. The thermometer-coded DAC comprises N capacitors. The N capacitors are respectively coupled to the N memory units. The N terminal voltages of the N capacitors are respectively controlled by the N control values.
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