Systems and method involving fast-acquisition lock features associated with phase locked loop circuitry
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United States of America Patent
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Jan 2, 2018
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app pub date -
Feb 24, 2017
filing date -
Nov 15, 2012
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Abstract
Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.
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