Level shifting circuit and integrated circuit
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United States of America Patent
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Jan 2, 2018
Grant Date -
N/A
app pub date -
Jan 26, 2017
filing date -
Jan 26, 2017
priority date (Note) -
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Abstract
In exemplary embodiments of the present disclosure, a level shifting circuit and an integrated circuit using the level shifting circuit are provided. Compared to the conventional level shifting circuit, the level shifting circuit herein further has another pair of PMOS transistors and another pair of NMOS transistors, wherein the other pair of the PMOS transistors is connected to the pair of the PMOS transistors, and the other pair of the NMOS transistors is connected to the pair of the NMOS transistors. PMOS and NMOS transistors of the level shifting circuit are protected, the lifetime of the level shifting circuit is increased, and the damage probability of the level shifting circuit is decreased. The other pair of the PMOS transistors being turned on can be operated in the saturation region rather than in the linear region, such that the operation speed of the level shifting circuit is enhanced.
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