Minimization of bias temperature instability (BTI) degradation in circuits
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United States of America Patent
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Jan 2, 2018
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app pub date -
Dec 4, 2014
filing date -
Dec 4, 2014
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Abstract
A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.
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