Importance

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Abstract

An apparatus having a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal, an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal, a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal, a controllable oscillator configured to receive the oscillator control signal and output a fifth clock, a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor, a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor, a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero, and a correlation circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.

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First Claim