Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry
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United States of America Patent
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Dec 26, 2017
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Jun 21, 2016
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Jun 22, 2015
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Abstract
Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
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