Integration of an auxiliary device with a clamping device in a transient voltage suppressor
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United States of America Patent
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Dec 26, 2017
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app pub date -
Nov 30, 2016
filing date -
Jan 31, 2014
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Abstract
Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.
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