Multipage program scheme for flash memory
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United States of America Patent
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Dec 26, 2017
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N/A
app pub date -
Sep 15, 2016
filing date -
Jul 21, 2010
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Abstract
A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline.
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