Compact and low loss Y-junction for submicron silicon waveguide
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United States of America Patent
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Dec 26, 2017
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Mar 1, 2017
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Nov 30, 2012
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Abstract
A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.
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