Phase locked loop circuit and method of frequency adjustment of injection locked frequency divider
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United States of America Patent
Stats
-
Dec 19, 2017
Issued Date -
N/A
app pub date -
Mar 13, 2014
filing date -
Mar 13, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In a PLL circuit, first an ILFD is connected to an output voltage Vtune from an LPF, thereby causing the ILFD to operate as an oscillator. The ILFD, a DIV, PFD, CP, and LPF form a PLL and thereby locking operations are initiated. When a predetermined time elapses, an output frequency from the ILFD converges into a certain value and the PLL is subjected to a locked state. After the locked state is reached, a sample hold circuit SH holds the output voltage Vtune from the loop filter as of that time and frequency adjustment of the ILFD is completed. Similar frequency adjustment is sequentially performed on other ILFDs.
First Claim
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International Classification(s)
- 2014 Application Filing Year
- H03L Class
- 712 Applications Filed
- 648 Patents Issued To-Date
- 91.02 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 2 Citation Count
- H03L Class
- 13.04 % this patent is cited more than
- 8 Age
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