Circuits incorporating integrated passive devices having inductances in 3D configurations and stacked with corresponding dies
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United States of America Patent
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Dec 19, 2017
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N/A
app pub date -
Feb 20, 2015
filing date -
Apr 2, 2014
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Abstract
A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.
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