Circuit and method for controlling MRAM cell bias voltages
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United States of America Patent
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Dec 19, 2017
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app pub date -
Dec 5, 2016
filing date -
May 17, 2012
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Abstract
A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
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