Processor, accelerator, and direct memory access controller within a processor core that each reads/writes a local synchronization flag area for parallel execution
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United States of America Patent
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Dec 19, 2017
Issued Date -
N/A
app pub date -
Oct 30, 2012
filing date -
Nov 4, 2011
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Abstract
It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.
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