Utilizing clock rate pipelining to generate code for multi-rate systems
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United States of America Patent
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Dec 19, 2017
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app pub date -
Jan 14, 2015
filing date -
Feb 28, 2013
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Abstract
A device generates a model associated with a multi-rate system. The multi-rate system includes a system associated with a clock rate and a sample rate, and the clock rate is greater than the sample rate. The device identifies the clock rate of the multi-rate system based on the model, and identifies a portion, of the model, associated with the sample rate. The device applies clock rate pipelining to adjust the sample rate associated with the portion of the model so that the sample rate substantially equals the clock rate, and generates code associated with the model and the applied clock rate pipelining.
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