Reference-frequency-insensitive phase locked loop
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 12, 2017
Issued Date -
N/A
app pub date -
Nov 29, 2016
filing date -
Aug 19, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. Opening a switch of the SLPF may hold the captured charge during a phase comparison and closing the switch may release the captured charge. The switch is controlled utilizing a control signal. By utilizing the SLPF in the phase locked loop, the phase locked loop may eliminate, at an output of the CHP, disturbance which is associated with duty cycle errors of the crystal clock signal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully