ESD protection circuit
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United States of America Patent
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Dec 12, 2017
Issued Date -
N/A
app pub date -
Dec 21, 2015
filing date -
Apr 17, 2015
priority date (Note) -
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Abstract
An ESD protection circuit is disclosed, in which an RC trigger circuit and a transmission gate are used for determination of ESD protection triggering, and a silicon-controlled rectifier for ESD current conductance. The RC trigger circuit and the transmission gate allow improved trigger efficiency. In addition, the silicon-controlled rectifier incorporates first and second resistors, which can be implemented to have very low resistance values and are therefore able to effectively prevent the occurrence of latch-up during normal operation, as well as pull-up and pull-down transistors which can make an additional contribution to latch-up inhibition when turned on.
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