Adaptive charge balanced edge termination

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United States of America Patent

PATENT NO 9842911
SERIAL NO

13484114

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Abstract

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In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.

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  • VISHAY-SILICONIX

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Inventor Name Address # of filed Patents Total Citations
Pattanayak, Deva N Saratoga, US 27 623
Tipirneni, Naveen Santa Clara, US 39 250

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  • 5 Citation Count
  • H01L Class
  • 18.50 % this patent is cited more than
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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges26979357140748325312788503629173801 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +050010001500200025003000350040004500500055006000650070007500800085009000950010000

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