Efficient constant multiplier implementation for programmable logic devices
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United States of America Patent
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Dec 12, 2017
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Jun 26, 2014
filing date -
Jun 26, 2014
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Abstract
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.
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