Integrated circuit, code generating method, and data exchange method

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United States of America Patent

PATENT NO 9838389
APP PUB NO 20150092777A1
SERIAL NO

14335957

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Abstract

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An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

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Patent Owner(s)

Patent OwnerAddress
PHISON ELECTRONICS CORPMIAOLI

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  • 2014 Application Filing Year
  • H04L Class
  • 29135 Applications Filed
  • 23333 Patents Issued To-Date
  • 80.09 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances201420152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Watanabe, Hiroshi Hsinchu, TW 915 12785

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  • 1 Citation Count
  • H04L Class
  • 11.47 % this patent is cited more than
  • 8 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges7723917103642621314694423014182001 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +025050075010001250150017502000225025002750300032503500375040004250

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