Low read current architecture for memory

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United States of America Patent

PATENT NO 9837149
SERIAL NO

15181009

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Abstract

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A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

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Patent OwnerAddress
UNITY SEMICONDUCTOR CORPORATION1050 ENTERPRISE WAY #700 C/O RAMBUS INC SUNNYVALE CA 94089

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bateman, Bruce Lynn Fremont, US 21 171
Chevallier, Christophe Palo Alto, US 141 2436
Rinerson, Darrell Cupertino, US 110 5317
Siau, Chang Hua Saratoga, US 70 1564

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