Counter, analogue to digital converter including the counter and image sensing device including the analogue to digital converter
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United States of America Patent
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Nov 28, 2017
Grant Date -
Nov 12, 2015
app pub date -
Sep 18, 2014
filing date -
May 7, 2014
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Abstract
A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.
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