Dummy bit line MOS capacitor and device using the same
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United States of America Patent
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Nov 21, 2017
Grant Date -
Mar 24, 2016
app pub date -
Dec 7, 2015
filing date -
Jul 17, 2012
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Abstract
A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
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