Current sensing using a metal-on-passivation layer on an integrated circuit die
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United States of America Patent
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Nov 21, 2017
Grant Date -
Feb 4, 2016
app pub date -
Aug 4, 2015
filing date -
Jun 14, 2012
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Abstract
A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor.
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