Incremental error detection and correction for memories
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United States of America Patent
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Nov 14, 2017
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app pub date -
Jul 19, 2015
filing date -
Jul 20, 2014
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Abstract
A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.
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