Termination trench structures for high-voltage split-gate MOS devices
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United States of America Patent
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Nov 14, 2017
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app pub date -
Mar 9, 2016
filing date -
Mar 9, 2016
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Abstract
Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SANKEN ELECTRIC CO LTD | 3-6-3 KITANO NIIZA-SHI SAITAMA-KEN 352-8666 | |
POLAR SEMICONDUCTOR LLC | 2800 E OLD SHAKOPEE ROAD BLOOMINGTON MN 55425 |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kamimura, Tatsuya | St. Louis Park, US | 17 | 29 |
Kosier, Steven | Lakeville, US | 16 | 75 |
Rankila, Don | Farmington, US | 8 | 30 |
West, Peter | Minneapolis, US | 20 | 229 |
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