Singulation method for semiconductor package with plating on side of connectors
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United States of America Patent
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Nov 14, 2017
Grant Date -
Aug 18, 2016
app pub date -
Apr 26, 2016
filing date -
Aug 31, 2010
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Abstract
A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.
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