Apparatus and method for achieving glitch-free clock domain crossing signals
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United States of America Patent
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Nov 14, 2017
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N/A
app pub date -
Nov 21, 2012
filing date -
Nov 22, 2011
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Abstract
A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
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