Semiconductor package and manufacturing method
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United States of America Patent
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Nov 7, 2017
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N/A
app pub date -
Oct 19, 2016
filing date -
Oct 19, 2016
priority date (Note) -
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Abstract
A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.
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